The semiconductor industry currently uses different types of semiconductor-based imagers including charge-coupled devices (CCD, as used herein throughout) and complementary metal oxide semiconductor (CMOS, as used herein throughout) imager devices. Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits is beneficial for many digital applications such as, for example, cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, and others.
A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photogenerated charge in a doped portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges typically from a doped floating diffusion region and produces an output signal which is periodically read-out through a row select access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the floating diffusion region or the floating diffusion region may be directly connected to or part of the photoconversion device. A transistor is also typically provided for resetting the diffusion region to a predetermined charge level before it receives the photoconverted charges.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the foregoing are hereby incorporated by reference herein in their entirety.
A known three-transistor (3T) CMOS active pixel sensor (APS) design used in many applications contains a photodiode for producing charges which are stored at a diffusion region, a reset transistor for resetting the diffusion region charge, a source follower transistor having a gate connected to the diffusion region for producing an output signal, and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. In a four-transistor (4T) CMOS configuration, a transfer transistor is employed to gate charges from the photodiode to the diffusion region.
Conventional floating diffusion regions in 3T and 4T pixel designs typically have a n+ highly-doped region to facilitate charge flow. In addition, these highly-doped n+ floating diffusion regions serve to provide a low resistance ohmic metal-semiconductor contact for charge transfer to the source follower transistor. However, these same highly-doped n+ regions create current leakage into the substrate due to high electric fields caused by the junction with a p-type region in which the n+ region is formed.
FIG. 1 illustrates a diagrammatic side sectional view of a CMOS image sensor four-transistor (4T) pixel employing a n+ highly-doped floating diffusion region 10.
The CMOS image sensor pixel 100 generally comprises a charge collection region 35 of a photodiode for collecting charges generated by light incident on the pixel and transfer transistor having a gate 60 for transferring photoelectric charges from the collection region 35 to a sensing node, typically a floating diffusion region 10. The floating diffusion region 10 is electrically connected to the gate of an output source follower transistor 40. The pixel 100 also includes a reset transistor having a gate 50 for resetting the floating diffusion region 10 to a predetermined voltage before charge is transferred thereto from the photodiode, the source follower transistor 40 which receives at its gate an electrical signal from the floating diffusion region 10, and a row select transistor 70 for selectively outputting a signal from the source follower transistor 40 to a column line 71 in response to a decoded row address driver signal applied to the gate of the transistor 70.
The exemplary pixel 100 of FIG. 1 employs a pinned photodiode having charge collection region 35. The pinned photodiode is termed such since the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted. The pinned photodiode has a photosensitive p-n junction region comprising a p-type surface layer 4 and a n-type photodiode region 35 within a p-type region 6. The two p-type regions 4, 6 cause the n-type photodiode region 35 to be fully depleted at a pinning voltage. Impurity doped source/drain regions, preferably having n-type conductivity, are provided about the transistor gates 50 and 60. The floating diffusion region 10 adjacent to transfer gates 51, 61 is a common source/drain region for a transfer transistor having gate 60 and the reset transistor having gate 50.
Conventionally, in forming the source/drain region for the transfer transistor having gate 60 and the reset transistor having gate 50, floating diffusion region 10 is formed by implanting dopants near the transfer and reset transistors and allowing the diffusion regions from each transistor to combine, e.g., to flow inwards toward each other, to ultimately form floating diffusion region 10.
Further, in a typical CMOS image sensor, trench isolation regions 8 formed in a p− region active layer 6 are used to isolate the pixels. The gate stacks for the pixel transistors are formed before or after the trench is etched. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow.
A translucent or transparent insulating layer 99 is typically formed over the pixel 100. Conventional processing methods are then carried out to form, for example, metal conductor 15 in the insulating layer to provide an electrical connection/contact to the floating diffusion region 10, and other wiring to connect gate lines and other connections in pixel 100. For example, the entire substrate surface may be covered with a passivation layer of e.g., silicon dioxide, BSG, PSG, or BPSG, which is planarized and etched to provide contact holes, which are then metallized to provide contacts to a photogate (if used in place of a photodiode), and diffusion node 10.
In conventional CMOS image sensors, electrons are generated by light incident externally and accumulates in the n-type photodiode region 35. These charges are transferred to the floating diffusion region 10 by the gate 60 of the transfer transistor. The source follower transistor 40 produces an output signal from the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 35. The maximum output signal increases with increased electron capacitance or acceptability of the photodiode 35. The electron capacity of pinned photodiodes typically depends on doping levels and the dopants implanted to form regions 4, 6, and 35.
Floating diffusion region 10 can lose some of the transferred charge across the p-n junction. Such current leakage lowers the available pixel output signal transmitted to the gate of source follower transistor 40. Typically, the floating diffusion region 10 includes a lightly-doped drain (LDD) n− region at areas extending slightly beneath the gates 50 and 60 and a heavily doped n+ region between the gates 50 and 60.
While the highly-doped n+ floating diffusion region 10 provides good charge transfer characteristics and a good ohmic contact to metal conductor 15, the highly-doped n+ floating diffusion region 10 also produces charge leakage into the p-type region 6 which diminishes the collected light signal that is transferred to the gate of the source follower transistor 40.
A floating diffusion region which is resistant to junction leakage and can still provide a good contact with metal conductor 15 is desired.